perfaware/part1: Support add instructions
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commit
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@ -8,7 +8,7 @@
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;
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; Please see https://computerenhance.com for further information
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;
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; ======================================================================== */
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; ========================================================================
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; ========================================================================
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; LISTING 37
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@ -8,7 +8,7 @@
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;
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; Please see https://computerenhance.com for further information
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;
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; ======================================================================== */
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; ========================================================================
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; ========================================================================
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; LISTING 38
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Binary file not shown.
@ -21,10 +21,12 @@ mov si, bx
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mov dh, al
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; 8-bit immediate-to-register
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mov cx, 12
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mov cx, -12
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mov cl, 12
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mov ch, -12
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; 16-bit immediate-to-register
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mov cx, 12
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mov cx, -12
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mov dx, 3948
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mov dx, -3948
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BIN
part1/listing_0041_add_sub_cmp_jnz
Normal file
BIN
part1/listing_0041_add_sub_cmp_jnz
Normal file
Binary file not shown.
121
part1/listing_0041_add_sub_cmp_jnz.asm
Normal file
121
part1/listing_0041_add_sub_cmp_jnz.asm
Normal file
@ -0,0 +1,121 @@
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; ========================================================================
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;
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; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
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;
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; This software is provided 'as-is', without any express or implied
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; warranty. In no event will the authors be held liable for any damages
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; arising from the use of this software.
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;
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; Please see https://computerenhance.com for further information
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;
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; ========================================================================
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; ========================================================================
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; LISTING 41
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; ========================================================================
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bits 16
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add bx, [bx+si]
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add bx, [bp]
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add si, 2
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add bp, 2
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add cx, 8
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add bx, [bp + 0]
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add cx, [bx + 2]
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add bh, [bp + si + 4]
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add di, [bp + di + 6]
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add [bx+si], bx
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add [bp], bx
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add [bp + 0], bx
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add [bx + 2], cx
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add [bp + si + 4], bh
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add [bp + di + 6], di
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add byte [bx], 34
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add word [bp + si + 1000], 29
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add ax, [bp]
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add al, [bx + si]
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add ax, bx
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add al, ah
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add ax, 1000
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add al, -30
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add al, 9
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sub bx, [bx+si]
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sub bx, [bp]
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sub si, 2
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sub bp, 2
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sub cx, 8
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sub bx, [bp + 0]
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sub cx, [bx + 2]
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sub bh, [bp + si + 4]
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sub di, [bp + di + 6]
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sub [bx+si], bx
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sub [bp], bx
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sub [bp + 0], bx
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sub [bx + 2], cx
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sub [bp + si + 4], bh
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sub [bp + di + 6], di
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sub byte [bx], 34
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sub word [bx + di], 29
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sub ax, [bp]
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sub al, [bx + si]
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sub ax, bx
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sub al, ah
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sub ax, 1000
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sub al, -30
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sub al, 9
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cmp bx, [bx+si]
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cmp bx, [bp]
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cmp si, 2
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cmp bp, 2
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cmp cx, 8
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cmp bx, [bp + 0]
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cmp cx, [bx + 2]
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cmp bh, [bp + si + 4]
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cmp di, [bp + di + 6]
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cmp [bx+si], bx
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cmp [bp], bx
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cmp [bp + 0], bx
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cmp [bx + 2], cx
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cmp [bp + si + 4], bh
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cmp [bp + di + 6], di
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cmp byte [bx], 34
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cmp word [4834], 29
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cmp ax, [bp]
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cmp al, [bx + si]
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cmp ax, bx
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cmp al, ah
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cmp ax, 1000
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cmp al, -30
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cmp al, 9
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test_label0:
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jnz test_label1
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jnz test_label0
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test_label1:
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jnz test_label0
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jnz test_label1
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label:
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je label
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jl label
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jle label
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jb label
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jbe label
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jp label
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jo label
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js label
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jne label
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jnl label
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jg label
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jnb label
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ja label
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jnp label
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jno label
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jns label
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loop label
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loopz label
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loopnz label
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jcxz label
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BIN
part1/listing_0042_completionist_decode
Normal file
BIN
part1/listing_0042_completionist_decode
Normal file
Binary file not shown.
425
part1/listing_0042_completionist_decode.asm
Normal file
425
part1/listing_0042_completionist_decode.asm
Normal file
@ -0,0 +1,425 @@
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; ========================================================================
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;
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; (C) Copyright 2023 by Molly Rocket, Inc., All Rights Reserved.
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;
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; This software is provided 'as-is', without any express or implied
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; warranty. In no event will the authors be held liable for any damages
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; arising from the use of this software.
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;
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; Please see https://computerenhance.com for further information
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;
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; ========================================================================
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; ========================================================================
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; LISTING 42
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; ========================================================================
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;
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; NOTE(casey): This is not meant to be a real compliance test for 8086
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; disassemblers. It's just a reasonable selection of opcodes and patterns
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; to use as a first pass in making sure a disassembler handles a large
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; cross-section of the encoding. To be absolutely certain you haven't
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; missed something, you would need a more exhaustive listing!
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;
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bits 16
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mov si, bx
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mov dh, al
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mov cl, 12
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mov ch, -12
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mov cx, 12
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mov cx, -12
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mov dx, 3948
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mov dx, -3948
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mov al, [bx + si]
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mov bx, [bp + di]
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mov dx, [bp]
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mov ah, [bx + si + 4]
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mov al, [bx + si + 4999]
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mov [bx + di], cx
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mov [bp + si], cl
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mov [bp], ch
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mov ax, [bx + di - 37]
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mov [si - 300], cx
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mov dx, [bx - 32]
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mov [bp + di], byte 7
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mov [di + 901], word 347
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mov bp, [5]
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mov bx, [3458]
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mov ax, [2555]
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mov ax, [16]
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mov [2554], ax
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mov [15], ax
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push word [bp + si]
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push word [3000]
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push word [bx + di - 30]
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push cx
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push ax
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push dx
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push cs
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pop word [bp + si]
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pop word [3]
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pop word [bx + di - 3000]
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pop sp
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pop di
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pop si
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pop ds
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xchg ax, [bp - 1000]
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xchg [bx + 50], bp
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xchg ax, ax
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xchg ax, dx
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xchg ax, sp
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xchg ax, si
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xchg ax, di
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xchg cx, dx
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xchg si, cx
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xchg cl, ah
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in al, 200
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in al, dx
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in ax, dx
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out 44, ax
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out dx, al
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xlat
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lea ax, [bx + di + 1420]
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lea bx, [bp - 50]
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lea sp, [bp - 1003]
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lea di, [bx + si - 7]
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lds ax, [bx + di + 1420]
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lds bx, [bp - 50]
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lds sp, [bp - 1003]
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lds di, [bx + si - 7]
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les ax, [bx + di + 1420]
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les bx, [bp - 50]
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les sp, [bp - 1003]
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les di, [bx + si - 7]
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lahf
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sahf
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pushf
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popf
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add cx, [bp]
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add dx, [bx + si]
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add [bp + di + 5000], ah
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add [bx], al
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add sp, 392
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add si, 5
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add ax, 1000
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add ah, 30
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add al, 9
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add cx, bx
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add ch, al
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adc cx, [bp]
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adc dx, [bx + si]
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adc [bp + di + 5000], ah
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adc [bx], al
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adc sp, 392
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adc si, 5
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adc ax, 1000
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adc ah, 30
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adc al, 9
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adc cx, bx
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adc ch, al
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inc ax
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inc cx
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inc dh
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inc al
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inc ah
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inc sp
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inc di
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inc byte [bp + 1002]
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inc word [bx + 39]
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inc byte [bx + si + 5]
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inc word [bp + di - 10044]
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inc word [9349]
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inc byte [bp]
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aaa
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daa
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sub cx, [bp]
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sub dx, [bx + si]
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sub [bp + di + 5000], ah
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sub [bx], al
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sub sp, 392
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sub si, 5
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sub ax, 1000
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sub ah, 30
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sub al, 9
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sub cx, bx
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sub ch, al
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sbb cx, [bp]
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sbb dx, [bx + si]
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sbb [bp + di + 5000], ah
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sbb [bx], al
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sbb sp, 392
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sbb si, 5
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sbb ax, 1000
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sbb ah, 30
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sbb al, 9
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sbb cx, bx
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sbb ch, al
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dec ax
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dec cx
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dec dh
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dec al
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dec ah
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dec sp
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dec di
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dec byte [bp + 1002]
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dec word [bx + 39]
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dec byte [bx + si + 5]
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dec word [bp + di - 10044]
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dec word [9349]
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dec byte [bp]
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neg ax
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neg cx
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neg dh
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neg al
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neg ah
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neg sp
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neg di
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neg byte [bp + 1002]
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neg word [bx + 39]
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neg byte [bx + si + 5]
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neg word [bp + di - 10044]
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neg word [9349]
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neg byte [bp]
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cmp bx, cx
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cmp dh, [bp + 390]
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cmp [bp + 2], si
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cmp bl, 20
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cmp byte [bx], 34
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cmp ax, 23909
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aas
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das
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mul al
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mul cx
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mul word [bp]
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mul byte [bx + di + 500]
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imul ch
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imul dx
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imul byte [bx]
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imul word [9483]
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aam
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div bl
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div sp
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div byte [bx + si + 2990]
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div word [bp + di + 1000]
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idiv ax
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idiv si
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idiv byte [bp + si]
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idiv word [bx + 493]
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aad
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cbw
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cwd
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not ah
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not bl
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not sp
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not si
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not word [bp]
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not byte [bp + 9905]
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shl ah, 1
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shr ax, 1
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sar bx, 1
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rol cx, 1
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ror dh, 1
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rcl sp, 1
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rcr bp, 1
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shl word [bp + 5], 1
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shr byte [bx + si - 199], 1
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sar byte [bx + di - 300], 1
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rol word [bp], 1
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ror word [4938], 1
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rcl byte [3], 1
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rcr word [bx], 1
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shl ah, cl
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shr ax, cl
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sar bx, cl
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rol cx, cl
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ror dh, cl
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rcl sp, cl
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rcr bp, cl
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shl word [bp + 5], cl
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shr word [bx + si - 199], cl
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sar byte [bx + di - 300], cl
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rol byte [bp], cl
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ror byte [4938], cl
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rcl byte [3], cl
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rcr word [bx], cl
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and al, ah
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and ch, cl
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and bp, si
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and di, sp
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and al, 93
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and ax, 20392
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and [bp + si + 10], ch
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and [bx + di + 1000], dx
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and bx, [bp]
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and cx, [4384]
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and byte [bp - 39], 239
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and word [bx + si - 4332], 10328
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test bx, cx
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test dh, [bp + 390]
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test [bp + 2], si
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test bl, 20
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test byte [bx], 34
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test ax, 23909
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or al, ah
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or ch, cl
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or bp, si
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or di, sp
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or al, 93
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or ax, 20392
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or [bp + si + 10], ch
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or [bx + di + 1000], dx
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or bx, [bp]
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or cx, [4384]
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or byte [bp - 39], 239
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or word [bx + si - 4332], 10328
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xor al, ah
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xor ch, cl
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xor bp, si
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xor di, sp
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xor al, 93
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xor ax, 20392
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xor [bp + si + 10], ch
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xor [bx + di + 1000], dx
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xor bx, [bp]
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xor cx, [4384]
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xor byte [bp - 39], 239
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xor word [bx + si - 4332], 10328
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rep movsb
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rep cmpsb
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rep scasb
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rep lodsb
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rep movsw
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rep cmpsw
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rep scasw
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rep lodsw
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; NOTE(casey): Special thanks (as always!) to Mārtiņš Možeiko for figuring out why NASM
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; wouldn't compile "rep stds" instructions. It was because it was a misprint in the 8086
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; manual! It was really just "rep stos", which of course is still in x64, and NASM
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; assembles it just fine.
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rep stosb
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rep stosw
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call [39201]
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call [bp - 100]
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call sp
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call ax
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jmp ax
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jmp di
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jmp [12]
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jmp [4395]
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ret -7
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ret 500
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ret
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label:
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je label
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jl label
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jle label
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jb label
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jbe label
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jp label
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jo label
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js label
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jne label
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jnl label
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jg label
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jnb label
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ja label
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jnp label
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jno label
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jns label
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loop label
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loopz label
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loopnz label
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jcxz label
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int 13
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int 3
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into
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iret
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clc
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cmc
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stc
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cld
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std
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cli
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sti
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hlt
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wait
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lock not byte [bp + 9905]
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lock xchg [100], al
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mov al, cs:[bx + si]
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mov bx, ds:[bp + di]
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mov dx, es:[bp]
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mov ah, ss:[bx + si + 4]
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and ss:[bp + si + 10], ch
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or ds:[bx + di + 1000], dx
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xor bx, es:[bp]
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cmp cx, es:[4384]
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test byte cs:[bp - 39], 239
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sbb word cs:[bx + si - 4332], 10328
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lock not byte CS:[bp + 9905]
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;
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; TODO(casey): I would like to uncomment this, but as far as I can tell, NASM doesn't recognize the ESC instruction :(
|
||||
; so even if I just force the assembler to output the bits here, our disasm will fail to assemble because it will (correctly!)
|
||||
; print the esc instruction and NASM will error because it doesn't know what that is.
|
||||
;
|
||||
; esc 938,ax
|
||||
;
|
||||
|
||||
;
|
||||
; TODO(casey): According to NASM, "rep movsb" is "not lockable". However the 8086 manual seems to think it is, and
|
||||
; even describes what happens when you you lock a rep: the lock is held for the duration of the rep operation. So...
|
||||
; yeah. Not sure why this doesn't work in NASM:
|
||||
;
|
||||
; lock rep movsb
|
||||
;
|
||||
207
part1/sim8086.c
207
part1/sim8086.c
@ -76,6 +76,9 @@ typedef enum S86_InstructionType {
|
||||
S86_InstructionType_MOVAccumToMem,
|
||||
S86_InstructionType_MOVRegOrMemToSegReg,
|
||||
S86_InstructionType_MOVSegRegToRegOrMem,
|
||||
S86_InstructionType_ADDRegOrMemToOrFromReg,
|
||||
S86_InstructionType_ADDImmediateToRegOrMem,
|
||||
S86_InstructionType_ADDImmediateToAccum,
|
||||
S86_InstructionType_Count,
|
||||
} S86_InstructionType;
|
||||
|
||||
@ -128,6 +131,21 @@ S86_Instruction const S86_INSTRUCTIONS[S86_InstructionType_Count] = {
|
||||
.op_bits0 = 0b1000'1100,
|
||||
.op_mask1 = 0b0010'0000,
|
||||
.op_bits1 = 0b0000'0000},
|
||||
|
||||
[S86_InstructionType_ADDRegOrMemToOrFromReg] = {.op_mask0 = 0b1111'1100,
|
||||
.op_bits0 = 0b0000'0000,
|
||||
.op_mask1 = 0b0000'0000,
|
||||
.op_bits1 = 0b0000'0000},
|
||||
|
||||
[S86_InstructionType_ADDImmediateToRegOrMem] = {.op_mask0 = 0b1111'1100,
|
||||
.op_bits0 = 0b1000'0000,
|
||||
.op_mask1 = 0b0011'1000,
|
||||
.op_bits1 = 0b0000'0000},
|
||||
|
||||
[S86_InstructionType_ADDImmediateToAccum] = {.op_mask0 = 0b1111'1110,
|
||||
.op_bits0 = 0b0000'0100,
|
||||
.op_mask1 = 0b0000'0000,
|
||||
.op_bits1 = 0b0000'0000},
|
||||
};
|
||||
|
||||
typedef struct S86_EffectiveAddressStr8 {
|
||||
@ -135,7 +153,7 @@ typedef struct S86_EffectiveAddressStr8 {
|
||||
size_t size;
|
||||
} S86_EffectiveAddressStr8;
|
||||
|
||||
S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it, uint8_t rm, uint8_t mod);
|
||||
S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it, uint8_t rm, uint8_t mod, uint8_t w);
|
||||
|
||||
// NOTE: Implementation
|
||||
// ============================================================================
|
||||
@ -282,7 +300,8 @@ void S86_PrintLnFmt(char const *fmt, ...)
|
||||
va_end(args);
|
||||
}
|
||||
|
||||
S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it, uint8_t rm, uint8_t mod)
|
||||
S86_Str8 REGISTER_FIELD_ENCODING[2][8];
|
||||
S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it, uint8_t rm, uint8_t mod, uint8_t w)
|
||||
{
|
||||
// NOTE: Calculate displacement
|
||||
// =========================================================================
|
||||
@ -295,43 +314,49 @@ S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it,
|
||||
} else if (mod == 0b01) { // Mem mode 8 bit displacement
|
||||
displacement = (int8_t)S86_BufferIteratorNextByte(buffer_it);
|
||||
} else {
|
||||
S86_ASSERT(mod == 0b00 /*Mem mode (no displacement)*/);
|
||||
S86_ASSERT(mod == 0b00 || mod == 0b11 /*Mem mode (no displacement)*/);
|
||||
}
|
||||
|
||||
// NOTE: Effective address calculation w/ displacement
|
||||
// =========================================================================
|
||||
S86_EffectiveAddressStr8 result = {0};
|
||||
result.data[result.size++] = '[';
|
||||
if (direct_address) {
|
||||
result.size += snprintf(result.data + result.size,
|
||||
sizeof(result.data) - result.size,
|
||||
"%s%d",
|
||||
displacement >= 0 ? "" : "-", displacement >= 0 ? displacement : -displacement);
|
||||
if (mod == 0b11) {
|
||||
S86_Str8 register_field = REGISTER_FIELD_ENCODING[w][rm];
|
||||
memcpy(result.data, register_field.data, register_field.size);
|
||||
result.size = register_field.size;
|
||||
} else {
|
||||
S86_Str8 base_calc = {0};
|
||||
switch (rm) {
|
||||
case 0b000: base_calc = S86_STR8("bx + si"); break;
|
||||
case 0b001: base_calc = S86_STR8("bx + di"); break;
|
||||
case 0b010: base_calc = S86_STR8("bp + si"); break;
|
||||
case 0b011: base_calc = S86_STR8("bp + di"); break;
|
||||
case 0b100: base_calc = S86_STR8("si"); break;
|
||||
case 0b101: base_calc = S86_STR8("di"); break;
|
||||
case 0b110: base_calc = S86_STR8("bp"); break;
|
||||
case 0b111: base_calc = S86_STR8("bx"); break;
|
||||
default: S86_ASSERT(!"Invalid rm value, must be 3 bits"); break;
|
||||
}
|
||||
|
||||
memcpy(result.data + result.size, base_calc.data, base_calc.size);
|
||||
result.size += S86_CAST(int)base_calc.size;
|
||||
|
||||
if ((mod == 0b01 || mod == 0b10) && displacement) {
|
||||
// NOTE: Effective address calculation w/ displacement
|
||||
// =========================================================================
|
||||
result.data[result.size++] = '[';
|
||||
if (direct_address) {
|
||||
result.size += snprintf(result.data + result.size,
|
||||
sizeof(result.data) - result.size,
|
||||
" %c %d",
|
||||
displacement >= 0 ? '+' : '-', displacement >= 0 ? displacement : -displacement);
|
||||
"%s%d",
|
||||
displacement >= 0 ? "" : "-", displacement >= 0 ? displacement : -displacement);
|
||||
} else {
|
||||
S86_Str8 base_calc = {0};
|
||||
switch (rm) {
|
||||
case 0b000: base_calc = S86_STR8("bx + si"); break;
|
||||
case 0b001: base_calc = S86_STR8("bx + di"); break;
|
||||
case 0b010: base_calc = S86_STR8("bp + si"); break;
|
||||
case 0b011: base_calc = S86_STR8("bp + di"); break;
|
||||
case 0b100: base_calc = S86_STR8("si"); break;
|
||||
case 0b101: base_calc = S86_STR8("di"); break;
|
||||
case 0b110: base_calc = S86_STR8("bp"); break;
|
||||
case 0b111: base_calc = S86_STR8("bx"); break;
|
||||
default: S86_ASSERT(!"Invalid rm value, must be 3 bits"); break;
|
||||
}
|
||||
|
||||
memcpy(result.data + result.size, base_calc.data, base_calc.size);
|
||||
result.size += S86_CAST(int)base_calc.size;
|
||||
|
||||
if ((mod == 0b01 || mod == 0b10) && displacement) {
|
||||
result.size += snprintf(result.data + result.size,
|
||||
sizeof(result.data) - result.size,
|
||||
" %c %d",
|
||||
displacement >= 0 ? '+' : '-', displacement >= 0 ? displacement : -displacement);
|
||||
}
|
||||
}
|
||||
result.data[result.size++] = ']';
|
||||
}
|
||||
result.data[result.size++] = ']';
|
||||
|
||||
S86_ASSERT(result.size < S86_ARRAY_UCOUNT(result.data));
|
||||
return result;
|
||||
@ -356,30 +381,23 @@ int main(int argc, char **argv)
|
||||
// NOTE: Sim8086
|
||||
// =========================================================================
|
||||
// Mapping from a 'reg' encoding to the register name.
|
||||
S86_Str8 const REGISTER_FIELD_ENCODING[2][8] = {
|
||||
[0b0] =
|
||||
{
|
||||
S86_STR8("al"),
|
||||
S86_STR8("cl"),
|
||||
S86_STR8("dl"),
|
||||
S86_STR8("bl"),
|
||||
S86_STR8("ah"),
|
||||
S86_STR8("ch"),
|
||||
S86_STR8("dh"),
|
||||
S86_STR8("bh"),
|
||||
},
|
||||
[0b1] =
|
||||
{
|
||||
S86_STR8("ax"),
|
||||
S86_STR8("cx"),
|
||||
S86_STR8("dx"),
|
||||
S86_STR8("bx"),
|
||||
S86_STR8("sp"),
|
||||
S86_STR8("bp"),
|
||||
S86_STR8("si"),
|
||||
S86_STR8("di"),
|
||||
},
|
||||
};
|
||||
REGISTER_FIELD_ENCODING[0b0][0] = S86_STR8("al");
|
||||
REGISTER_FIELD_ENCODING[0b0][1] = S86_STR8("cl");
|
||||
REGISTER_FIELD_ENCODING[0b0][2] = S86_STR8("dl");
|
||||
REGISTER_FIELD_ENCODING[0b0][3] = S86_STR8("bl");
|
||||
REGISTER_FIELD_ENCODING[0b0][4] = S86_STR8("ah");
|
||||
REGISTER_FIELD_ENCODING[0b0][5] = S86_STR8("ch");
|
||||
REGISTER_FIELD_ENCODING[0b0][6] = S86_STR8("dh");
|
||||
REGISTER_FIELD_ENCODING[0b0][7] = S86_STR8("bh");
|
||||
|
||||
REGISTER_FIELD_ENCODING[0b1][0] = S86_STR8("ax");
|
||||
REGISTER_FIELD_ENCODING[0b1][1] = S86_STR8("cx");
|
||||
REGISTER_FIELD_ENCODING[0b1][2] = S86_STR8("dx");
|
||||
REGISTER_FIELD_ENCODING[0b1][3] = S86_STR8("bx");
|
||||
REGISTER_FIELD_ENCODING[0b1][4] = S86_STR8("sp");
|
||||
REGISTER_FIELD_ENCODING[0b1][5] = S86_STR8("bp");
|
||||
REGISTER_FIELD_ENCODING[0b1][6] = S86_STR8("si");
|
||||
REGISTER_FIELD_ENCODING[0b1][7] = S86_STR8("di");
|
||||
|
||||
// NOTE: Decode assembly
|
||||
// =========================================================================
|
||||
@ -430,6 +448,7 @@ int main(int argc, char **argv)
|
||||
|
||||
switch (instruction_type) {
|
||||
|
||||
case S86_InstructionType_ADDRegOrMemToOrFromReg: /*FALLTHRU*/
|
||||
case S86_InstructionType_MOVRegOrMemToOrFromReg: {
|
||||
// NOTE: Instruction does not have opcode bits in the 2nd byte
|
||||
S86_ASSERT(op_code_size == 1);
|
||||
@ -446,55 +465,90 @@ int main(int argc, char **argv)
|
||||
S86_ASSERT(reg < 8);
|
||||
S86_ASSERT(rm < 8);
|
||||
|
||||
S86_Str8 op = {0};
|
||||
if (instruction_type == S86_InstructionType_MOVRegOrMemToOrFromReg) {
|
||||
op = S86_STR8("mov");
|
||||
} else {
|
||||
op = S86_STR8("add");
|
||||
S86_ASSERT(instruction_type == S86_InstructionType_ADDRegOrMemToOrFromReg);
|
||||
}
|
||||
|
||||
if (mod == 0b11) {
|
||||
// NOTE: Register-to-register move
|
||||
// =========================================================
|
||||
S86_Str8 src_op = REGISTER_FIELD_ENCODING[w][d ? rm : reg];
|
||||
S86_Str8 dest_op = REGISTER_FIELD_ENCODING[w][d ? reg : rm];
|
||||
S86_PrintLnFmt("mov %.*s, %.*s", S86_STR8_FMT(dest_op), S86_STR8_FMT(src_op));
|
||||
S86_PrintLnFmt("%.*s %.*s, %.*s", S86_STR8_FMT(op), S86_STR8_FMT(dest_op), S86_STR8_FMT(src_op));
|
||||
} else {
|
||||
// NOTE: Memory mode w/ effective address calculation
|
||||
// =========================================================
|
||||
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod);
|
||||
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod, w);
|
||||
S86_Str8 addr = { .data = effective_address.data, .size = effective_address.size };
|
||||
S86_Str8 dest_op = d ? REGISTER_FIELD_ENCODING[w][reg] : addr;
|
||||
S86_Str8 src_op = d ? addr : REGISTER_FIELD_ENCODING[w][reg];
|
||||
S86_PrintLnFmt("mov %.*s, %.*s", S86_STR8_FMT(dest_op), S86_STR8_FMT(src_op));
|
||||
S86_PrintLnFmt("%.*s %.*s, %.*s", S86_STR8_FMT(op), S86_STR8_FMT(dest_op), S86_STR8_FMT(src_op));
|
||||
}
|
||||
} break;
|
||||
|
||||
case S86_InstructionType_ADDImmediateToRegOrMem: /*FALLTHRU*/
|
||||
case S86_InstructionType_MOVImmediateToRegOrMem: {
|
||||
S86_ASSERT(op_code_size == 2);
|
||||
uint8_t w = (op_code_bytes[0] & 0b0000'0001) >> 0;
|
||||
uint8_t s = (op_code_bytes[0] & 0b0000'0010) >> 1;
|
||||
uint8_t mod = (op_code_bytes[1] & 0b1100'0000) >> 6;
|
||||
uint8_t rm = (op_code_bytes[1] & 0b0000'0111) >> 0;
|
||||
S86_ASSERT(w < 2);
|
||||
S86_ASSERT(mod < 4);
|
||||
S86_ASSERT(rm < 8);
|
||||
S86_ASSERT(mod != 0b11); // NOTE: Op is IMM->Reg, register-to-register not permitted
|
||||
|
||||
// NOTE: Memory mode w/ effective address calculation
|
||||
// =========================================================
|
||||
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod);
|
||||
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod, w);
|
||||
|
||||
// NOTE: Parse data payload
|
||||
// =============================================================
|
||||
uint16_t data = S86_BufferIteratorNextByte(&buffer_it);
|
||||
uint16_t data = S86_BufferIteratorNextByte(&buffer_it);
|
||||
bool sign_extend_8bit_data = false;
|
||||
if (w) { // 16 bit data
|
||||
uint8_t data_hi = S86_BufferIteratorNextByte(&buffer_it);
|
||||
data |= (uint16_t)(data_hi) << 8;
|
||||
if (instruction_type == S86_InstructionType_ADDImmediateToRegOrMem && s) {
|
||||
sign_extend_8bit_data = true;
|
||||
} else {
|
||||
uint8_t data_hi = S86_BufferIteratorNextByte(&buffer_it);
|
||||
data |= (uint16_t)(data_hi) << 8;
|
||||
}
|
||||
}
|
||||
|
||||
S86_Str8 op = {0};
|
||||
if (instruction_type == S86_InstructionType_MOVImmediateToRegOrMem) {
|
||||
S86_ASSERT(mod != 0b11); // NOTE: Op is IMM->Reg, register-to-register not permitted
|
||||
op = S86_STR8("mov");
|
||||
} else {
|
||||
S86_ASSERT(instruction_type == S86_InstructionType_ADDImmediateToRegOrMem);
|
||||
op = S86_STR8("add");
|
||||
}
|
||||
|
||||
// NOTE: Disassemble
|
||||
// =========================================================
|
||||
S86_PrintLnFmt("mov %.*s, %s %u", effective_address.size, effective_address.data, w ? "word" : "byte", data);
|
||||
if (instruction_type == S86_InstructionType_MOVImmediateToRegOrMem) {
|
||||
S86_PrintLnFmt("%.*s %.*s, %s %u", S86_STR8_FMT(op), effective_address.size, effective_address.data, w ? "word" : "byte", data);
|
||||
} else {
|
||||
if (sign_extend_8bit_data) {
|
||||
S86_PrintLnFmt("%.*s %.*s, %d", S86_STR8_FMT(op), effective_address.size, effective_address.data, (int16_t)data);
|
||||
} else {
|
||||
S86_PrintLnFmt("%.*s %.*s, %u", S86_STR8_FMT(op), effective_address.size, effective_address.data, data);
|
||||
}
|
||||
}
|
||||
} break;
|
||||
|
||||
case S86_InstructionType_ADDImmediateToAccum: /*FALLTHRU*/
|
||||
case S86_InstructionType_MOVImmediateToReg: {
|
||||
// NOTE: Parse opcode control bits
|
||||
// =============================================================
|
||||
S86_ASSERT(op_code_size == 1);
|
||||
uint8_t w = (op_code_bytes[0] & 0b0000'1000) >> 3;
|
||||
uint8_t w = 0;
|
||||
if (instruction_type == S86_InstructionType_ADDImmediateToAccum) {
|
||||
w = (op_code_bytes[0] & 0b0000'0001) >> 0;
|
||||
} else {
|
||||
w = (op_code_bytes[0] & 0b0000'1000) >> 3;
|
||||
}
|
||||
uint8_t reg = (op_code_bytes[0] & 0b0000'0111) >> 0;
|
||||
|
||||
// NOTE: Parse data payload
|
||||
@ -507,8 +561,23 @@ int main(int argc, char **argv)
|
||||
|
||||
// NOTE: Disassemble
|
||||
// =============================================================
|
||||
S86_Str8 dest_register = REGISTER_FIELD_ENCODING[w][reg];
|
||||
S86_PrintLnFmt("mov %.*s, %d", S86_STR8_FMT(dest_register), (int16_t)data);
|
||||
S86_Str8 op = {0};
|
||||
S86_Str8 dest_register = {0};
|
||||
if (instruction_type == S86_InstructionType_MOVImmediateToReg) {
|
||||
op = S86_STR8("mov");
|
||||
dest_register = REGISTER_FIELD_ENCODING[w][reg];
|
||||
} else {
|
||||
S86_ASSERT(instruction_type == S86_InstructionType_ADDImmediateToAccum);
|
||||
op = S86_STR8("add");
|
||||
if (w) {
|
||||
dest_register = S86_STR8("ax");
|
||||
} else {
|
||||
data = (uint16_t)(int8_t)data; // Sign extension
|
||||
dest_register = S86_STR8("al");
|
||||
}
|
||||
}
|
||||
|
||||
S86_PrintLnFmt("%.*s %.*s, %d", S86_STR8_FMT(op), S86_STR8_FMT(dest_register), (int16_t)data);
|
||||
} break;
|
||||
|
||||
case S86_InstructionType_MOVAccumToMem: /*FALLTHRU*/
|
||||
|
||||
BIN
project.rdbg
BIN
project.rdbg
Binary file not shown.
Loading…
Reference in New Issue
Block a user