perfaware/part1: Add support for NOT/MUL/IDIV operands
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parent
7600b58188
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657543d584
103
part1/sim8086.c
103
part1/sim8086.c
@ -133,6 +133,24 @@ typedef enum S86_InstructionType {
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S86_InstructionType_AAS,
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S86_InstructionType_DAS,
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S86_InstructionType_MUL,
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S86_InstructionType_IMUL,
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S86_InstructionType_AAM,
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S86_InstructionType_DIV,
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S86_InstructionType_IDIV,
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S86_InstructionType_AAD,
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S86_InstructionType_CBW,
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S86_InstructionType_CWD,
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S86_InstructionType_NOT,
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S86_InstructionType_SHL_SAL,
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S86_InstructionType_SHR,
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S86_InstructionType_SAR,
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S86_InstructionType_ROL,
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S86_InstructionType_ROR,
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S86_InstructionType_RCL,
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S86_InstructionType_RCR,
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S86_InstructionType_CMPRegOrMemAndReg,
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S86_InstructionType_CMPImmediateWithRegOrMem,
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S86_InstructionType_CMPImmediateWithAccum,
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@ -458,7 +476,7 @@ int main(int argc, char **argv)
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REGISTER_FIELD_ENCODING[0b1][6] = S86_STR8("si");
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REGISTER_FIELD_ENCODING[0b1][7] = S86_STR8("di");
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S86_Instruction const S86_INSTRUCTIONS[S86_InstructionType_Count] = {
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S86_Instruction const S86_INSTRUCTIONS[] = {
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[S86_InstructionType_MOVRegOrMemToOrFromReg] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1000'1000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("mov")},
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[S86_InstructionType_MOVImmediateToRegOrMem] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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@ -566,17 +584,52 @@ int main(int argc, char **argv)
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[S86_InstructionType_NEG] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0001'1000, .mnemonic = S86_STR8("neg")},
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[S86_InstructionType_AAS] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0011'1111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("aas")},
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[S86_InstructionType_DAS] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0010'1111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("das")},
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[S86_InstructionType_CMPRegOrMemAndReg] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0011'1000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("cmp")},
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[S86_InstructionType_CMPImmediateWithRegOrMem] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1000'0000, .op_bits1 = 0b0011'1000, .mnemonic = S86_STR8("cmp")},
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[S86_InstructionType_CMPImmediateWithAccum] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0011'1100, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("cmp")},
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[S86_InstructionType_AAS] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0011'1111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("aas")},
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[S86_InstructionType_DAS] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0010'1111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("das")},
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[S86_InstructionType_MUL] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0010'0000, .mnemonic = S86_STR8("mul")},
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[S86_InstructionType_IMUL] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0010'1000, .mnemonic = S86_STR8("imul")},
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[S86_InstructionType_AAM] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b1111'1111,
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.op_bits0 = 0b1101'0100, .op_bits1 = 0b0000'1010, .mnemonic = S86_STR8("aam")},
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[S86_InstructionType_DIV] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0011'0000, .mnemonic = S86_STR8("div")},
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[S86_InstructionType_IDIV] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0011'1000, .mnemonic = S86_STR8("idiv")},
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[S86_InstructionType_AAD] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b1111'1111,
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.op_bits0 = 0b1101'0101, .op_bits1 = 0b0000'1010, .mnemonic = S86_STR8("aad")},
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[S86_InstructionType_CBW] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("cbw")},
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[S86_InstructionType_CWD] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1001, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("cwd")},
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[S86_InstructionType_NOT] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1111'0110, .op_bits1 = 0b0001'0000, .mnemonic = S86_STR8("not")},
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[S86_InstructionType_SHL_SAL] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0010'0000, .mnemonic = S86_STR8("shl")},
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[S86_InstructionType_SHR] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0010'1000, .mnemonic = S86_STR8("shr")},
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[S86_InstructionType_SAR] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0011'1000, .mnemonic = S86_STR8("sar")},
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[S86_InstructionType_ROL] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("rol")},
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[S86_InstructionType_ROR] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0000'1000, .mnemonic = S86_STR8("ror")},
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[S86_InstructionType_RCL] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0001'0000, .mnemonic = S86_STR8("rcl")},
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[S86_InstructionType_RCR] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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.op_bits0 = 0b1101'0000, .op_bits1 = 0b0001'1000, .mnemonic = S86_STR8("rcr")},
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[S86_InstructionType_JE_JZ] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0111'0100, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("je")},
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[S86_InstructionType_JL_JNGE] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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@ -680,6 +733,18 @@ int main(int argc, char **argv)
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S86_Print(instruction->mnemonic);
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switch (instruction_type) {
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case S86_InstructionType_NOT: /*FALLTHRU*/
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case S86_InstructionType_SHL_SAL: /*FALLTHRU*/
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case S86_InstructionType_SHR: /*FALLTHRU*/
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case S86_InstructionType_SAR: /*FALLTHRU*/
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case S86_InstructionType_ROL: /*FALLTHRU*/
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case S86_InstructionType_ROR: /*FALLTHRU*/
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case S86_InstructionType_RCL: /*FALLTHRU*/
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case S86_InstructionType_RCR: /*FALLTHRU*/
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case S86_InstructionType_MUL: /*FALLTHRU*/
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case S86_InstructionType_IMUL: /*FALLTHRU*/
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case S86_InstructionType_DIV: /*FALLTHRU*/
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case S86_InstructionType_IDIV: /*FALLTHRU*/
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case S86_InstructionType_INCRegOrMem: /*FALLTHRU*/
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case S86_InstructionType_DECRegOrMem: /*FALLTHRU*/
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case S86_InstructionType_NEG: /*FALLTHRU*/
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@ -693,14 +758,30 @@ int main(int argc, char **argv)
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uint8_t w = 1;
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if (instruction_type == S86_InstructionType_INCRegOrMem ||
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instruction_type == S86_InstructionType_DECRegOrMem ||
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instruction_type == S86_InstructionType_NEG) {
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instruction_type == S86_InstructionType_NEG ||
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instruction_type == S86_InstructionType_MUL ||
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instruction_type == S86_InstructionType_MUL ||
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instruction_type == S86_InstructionType_IMUL ||
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instruction_type == S86_InstructionType_DIV ||
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instruction_type == S86_InstructionType_IDIV ||
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(instruction_type >= S86_InstructionType_NOT &&
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instruction_type <= S86_InstructionType_RCR)) {
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w = op_code_bytes[0] & 0b0000'0001;
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}
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S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod, w);
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if (effective_address.data[0] == '[')
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S86_PrintFmt(" %s", w ? "word" : "byte");
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S86_PrintLnFmt(" %.*s", S86_STR8_FMT(effective_address));
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S86_PrintFmt(" %.*s", S86_STR8_FMT(effective_address));
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// NOTE: Bit shifts use 'v' to indicate if shift distance should
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// come from cl register otherwise bitshift by 1
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if (instruction_type >= S86_InstructionType_SHL_SAL && instruction_type <= S86_InstructionType_RCR) {
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uint8_t v = (op_code_bytes[0] & 0b0000'0010) >> 1;
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S86_PrintFmt(", %s", v ? "cl" : "1");
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}
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S86_Print(S86_STR8("\n"));
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} break;
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case S86_InstructionType_DECReg: /*FALLTHRU*/
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@ -954,7 +1035,11 @@ int main(int argc, char **argv)
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instruction_type == S86_InstructionType_DAA ||
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instruction_type == S86_InstructionType_AAA ||
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instruction_type == S86_InstructionType_DAS ||
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instruction_type == S86_InstructionType_AAS) {
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instruction_type == S86_InstructionType_AAS ||
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instruction_type == S86_InstructionType_AAM ||
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instruction_type == S86_InstructionType_AAD ||
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instruction_type == S86_InstructionType_CBW ||
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instruction_type == S86_InstructionType_CWD) {
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// NOTE: Mnemonic instruction only, already printed
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S86_Print(S86_STR8("\n"));
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} else {
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BIN
project.rdbg
BIN
project.rdbg
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