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perfaware/part1: Add support for INC

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This commit is contained in:
doyle 2023-03-19 14:39:21 +11:00
parent be70547166
commit 4652f9e832
1 changed files with 140 additions and 125 deletions
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35
part1/sim8086.c
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@ -112,6 +112,9 @@ typedef enum S86_InstructionType {
S86_InstructionType_ADCImmediateToRegOrMem,
S86_InstructionType_ADCImmediateToAccum,
S86_InstructionType_INCRegOrMem,
S86_InstructionType_INCReg,
S86_InstructionType_SUBRegOrMemToOrFromReg,
S86_InstructionType_SUBImmediateFromRegOrMem,
S86_InstructionType_SUBImmediateFromAccum,
@ -518,6 +521,12 @@ int main(int argc, char **argv)
[S86_InstructionType_ADCImmediateToAccum] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0000'0000,
.op_bits0 = 0b0001'0100, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("adc")},
[S86_InstructionType_INCRegOrMem] = {.op_mask0 = 0b1111'1110, .op_mask1 = 0b0011'1000,
.op_bits0 = 0b1111'1110, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("inc")},
[S86_InstructionType_INCReg] = {.op_mask0 = 0b1111'1000, .op_mask1 = 0b0000'0000,
.op_bits0 = 0b0100'0000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("inc")},
[S86_InstructionType_SUBRegOrMemToOrFromReg] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0000'0000,
.op_bits0 = 0b0010'1000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("sub")},
[S86_InstructionType_SUBImmediateFromRegOrMem] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
@ -634,15 +643,21 @@ int main(int argc, char **argv)
switch (instruction_type) {
case S86_InstructionType_POPRegOrMem: /*FALLTHRU*/
case S86_InstructionType_INCRegOrMem: /*FALLTHRU*/
case S86_InstructionType_PUSHRegOrMem: {
S86_ASSERT(op_code_size == 2);
uint8_t mod = (op_code_bytes[1] & 0b1100'0000) >> 6;
uint8_t rm = (op_code_bytes[1] & 0b0000'0111) >> 0;
uint8_t w = instruction_type == S86_InstructionType_INCRegOrMem ? (op_code_bytes[0] & 0b0000'0001) : 1;
S86_ASSERT(mod < 4); S86_ASSERT(rm < 8);
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod, 0 /*w*/);
S86_PrintLnFmt(" word %.*s", S86_STR8_FMT(effective_address));
S86_EffectiveAddressStr8 effective_address = S86_EffectiveAddressCalc(&buffer_it, rm, mod, w);
if (effective_address.data[0] == '[')
S86_PrintFmt(" %s", w ? "word" : "byte");
S86_PrintLnFmt(" %.*s", S86_STR8_FMT(effective_address));
} break;
case S86_InstructionType_INCReg: /*FALLTHRU*/
case S86_InstructionType_XCHGRegWithAccum: /*FALLTHRU*/
case S86_InstructionType_PUSHReg: /*FALLTHRU*/
case S86_InstructionType_POPReg: /*FALLTHRU*/
case S86_InstructionType_PUSHSegReg: /*FALLTHRU*/
@ -650,7 +665,9 @@ int main(int argc, char **argv)
S86_ASSERT(op_code_size == 1);
S86_Str8 reg_name = {0};
if (instruction_type == S86_InstructionType_PUSHReg ||
instruction_type == S86_InstructionType_POPReg) {
instruction_type == S86_InstructionType_POPReg ||
instruction_type == S86_InstructionType_INCReg ||
instruction_type == S86_InstructionType_XCHGRegWithAccum) {
uint8_t reg = (op_code_bytes[0] & 0b0000'0111) >> 0;
reg_name = REGISTER_FIELD_ENCODING[/*w*/1][reg];
} else {
@ -659,6 +676,10 @@ int main(int argc, char **argv)
uint8_t sr = (op_code_bytes[0] & 0b0001'1000) >> 3;
reg_name = SEGMENT_REGISTER_NAME[sr];
}
if (instruction_type == S86_InstructionType_XCHGRegWithAccum)
S86_Print(S86_STR8(" ax,"));
S86_PrintLnFmt(" %.*s", S86_STR8_FMT(reg_name));
} break;
@ -815,13 +836,6 @@ int main(int argc, char **argv)
S86_PrintLnFmt(" %.*s, %d", S86_STR8_FMT(dest_register), (int16_t)data);
} break;
case S86_InstructionType_XCHGRegWithAccum: {
S86_ASSERT(op_code_size == 1);
uint8_t reg = (op_code_bytes[0] & 0b0000'0111) >> 0;
S86_Str8 reg_name = REGISTER_FIELD_ENCODING[1 /*w*/][reg];
S86_PrintLnFmt(" ax, %.*s", S86_STR8_FMT(reg_name));
} break;
case S86_InstructionType_INFixedPort: /*FALLTHRU*/
case S86_InstructionType_INVariablePort: /*FALLTHRU*/
case S86_InstructionType_OUTFixedPort: /*FALLTHRU*/
@ -885,6 +899,7 @@ int main(int argc, char **argv)
// NOTE: Mnemonic instruction only, already printed
S86_Print(S86_STR8("\n"));
} else {
S86_Print(S86_STR8("\n"));
S86_ASSERT(!"Unhandled instruction");
}
} break;