sim8086: Store and print from combined struct, S86_Opcode
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1499
part1/sim8086.c
1499
part1/sim8086.c
File diff suppressed because it is too large
Load Diff
477
part1/sim8086.h
477
part1/sim8086.h
@ -1,167 +1,255 @@
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// NOTE: Sim8086
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// NOTE: Sim8086
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// ============================================================================
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// ============================================================================
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typedef enum S86_InstructionType {
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typedef enum S86_OpDecodeType {
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S86_InstructionType_MOVRegOrMemToOrFromReg,
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S86_OpDecodeType_MOVRegOrMemToOrFromReg,
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S86_InstructionType_MOVImmediateToRegOrMem,
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S86_OpDecodeType_MOVImmediateToRegOrMem,
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S86_InstructionType_MOVImmediateToReg,
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S86_OpDecodeType_MOVImmediateToReg,
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S86_InstructionType_MOVMemToAccum,
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S86_OpDecodeType_MOVMemToAccum,
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S86_InstructionType_MOVAccumToMem,
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S86_OpDecodeType_MOVAccumToMem,
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S86_InstructionType_MOVRegOrMemToSegReg,
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S86_OpDecodeType_MOVRegOrMemToSegReg,
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S86_InstructionType_MOVSegRegToRegOrMem,
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S86_OpDecodeType_MOVSegRegToRegOrMem,
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S86_InstructionType_PUSHRegOrMem,
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S86_OpDecodeType_PUSHRegOrMem,
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S86_InstructionType_PUSHReg,
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S86_OpDecodeType_PUSHReg,
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S86_InstructionType_PUSHSegReg,
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S86_OpDecodeType_PUSHSegReg,
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S86_InstructionType_POPRegOrMem,
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S86_OpDecodeType_POPRegOrMem,
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S86_InstructionType_POPReg,
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S86_OpDecodeType_POPReg,
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S86_InstructionType_POPSegReg,
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S86_OpDecodeType_POPSegReg,
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S86_InstructionType_XCHGRegOrMemWithReg,
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S86_OpDecodeType_XCHGRegOrMemWithReg,
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S86_InstructionType_XCHGRegWithAccum,
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S86_OpDecodeType_XCHGRegWithAccum,
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S86_InstructionType_INFixedPort,
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S86_OpDecodeType_INFixedPort,
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S86_InstructionType_INVariablePort,
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S86_OpDecodeType_INVariablePort,
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S86_InstructionType_OUTFixedPort,
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S86_OpDecodeType_OUTFixedPort,
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S86_InstructionType_OUTVariablePort,
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S86_OpDecodeType_OUTVariablePort,
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S86_InstructionType_XLAT,
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S86_OpDecodeType_XLAT,
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S86_InstructionType_LEA,
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S86_OpDecodeType_LEA,
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S86_InstructionType_LDS,
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S86_OpDecodeType_LDS,
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S86_InstructionType_LES,
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S86_OpDecodeType_LES,
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S86_InstructionType_LAHF,
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S86_OpDecodeType_LAHF,
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S86_InstructionType_SAHF,
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S86_OpDecodeType_SAHF,
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S86_InstructionType_PUSHF,
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S86_OpDecodeType_PUSHF,
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S86_InstructionType_POPF,
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S86_OpDecodeType_POPF,
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S86_InstructionType_ADDRegOrMemToOrFromReg,
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S86_OpDecodeType_ADDRegOrMemToOrFromReg,
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S86_InstructionType_ADDImmediateToRegOrMem,
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S86_OpDecodeType_ADDImmediateToRegOrMem,
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S86_InstructionType_ADDImmediateToAccum,
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S86_OpDecodeType_ADDImmediateToAccum,
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S86_InstructionType_ADCRegOrMemWithRegToEither,
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S86_OpDecodeType_ADCRegOrMemWithRegToEither,
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S86_InstructionType_ADCImmediateToRegOrMem,
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S86_OpDecodeType_ADCImmediateToRegOrMem,
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S86_InstructionType_ADCImmediateToAccum,
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S86_OpDecodeType_ADCImmediateToAccum,
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S86_InstructionType_INCRegOrMem,
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S86_OpDecodeType_INCRegOrMem,
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S86_InstructionType_INCReg,
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S86_OpDecodeType_INCReg,
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S86_InstructionType_AAA,
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S86_OpDecodeType_AAA,
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S86_InstructionType_DAA,
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S86_OpDecodeType_DAA,
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S86_InstructionType_SUBRegOrMemToOrFromReg,
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S86_OpDecodeType_SUBRegOrMemToOrFromReg,
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S86_InstructionType_SUBImmediateFromRegOrMem,
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S86_OpDecodeType_SUBImmediateFromRegOrMem,
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S86_InstructionType_SUBImmediateFromAccum,
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S86_OpDecodeType_SUBImmediateFromAccum,
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S86_InstructionType_SBBRegOrMemAndRegToEither,
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S86_OpDecodeType_SBBRegOrMemAndRegToEither,
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S86_InstructionType_SBBImmediateFromRegOrMem,
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S86_OpDecodeType_SBBImmediateFromRegOrMem,
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S86_InstructionType_SBBImmediateFromAccum,
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S86_OpDecodeType_SBBImmediateFromAccum,
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S86_InstructionType_DECRegOrMem,
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S86_OpDecodeType_DECRegOrMem,
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S86_InstructionType_DECReg,
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S86_OpDecodeType_DECReg,
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S86_InstructionType_NEG,
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S86_OpDecodeType_NEG,
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S86_InstructionType_CMPRegOrMemAndReg,
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S86_OpDecodeType_CMPRegOrMemAndReg,
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S86_InstructionType_CMPImmediateWithRegOrMem,
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S86_OpDecodeType_CMPImmediateWithRegOrMem,
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S86_InstructionType_CMPImmediateWithAccum,
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S86_OpDecodeType_CMPImmediateWithAccum,
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S86_InstructionType_AAS,
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S86_OpDecodeType_AAS,
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S86_InstructionType_DAS,
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S86_OpDecodeType_DAS,
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S86_InstructionType_MUL,
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S86_OpDecodeType_MUL,
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S86_InstructionType_IMUL,
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S86_OpDecodeType_IMUL,
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S86_InstructionType_AAM,
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S86_OpDecodeType_AAM,
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S86_InstructionType_DIV,
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S86_OpDecodeType_DIV,
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S86_InstructionType_IDIV,
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S86_OpDecodeType_IDIV,
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S86_InstructionType_AAD,
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S86_OpDecodeType_AAD,
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S86_InstructionType_CBW,
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S86_OpDecodeType_CBW,
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S86_InstructionType_CWD,
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S86_OpDecodeType_CWD,
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S86_InstructionType_NOT,
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S86_OpDecodeType_NOT,
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S86_InstructionType_SHL_SAL,
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S86_OpDecodeType_SHL_SAL,
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S86_InstructionType_SHR,
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S86_OpDecodeType_SHR,
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S86_InstructionType_SAR,
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S86_OpDecodeType_SAR,
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S86_InstructionType_ROL,
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S86_OpDecodeType_ROL,
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S86_InstructionType_ROR,
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S86_OpDecodeType_ROR,
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S86_InstructionType_RCL,
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S86_OpDecodeType_RCL,
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S86_InstructionType_RCR,
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S86_OpDecodeType_RCR,
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S86_InstructionType_ANDRegWithMemToEither,
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S86_OpDecodeType_ANDRegWithMemToEither,
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S86_InstructionType_ANDImmediateToRegOrMem,
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S86_OpDecodeType_ANDImmediateToRegOrMem,
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S86_InstructionType_ANDImmediateToAccum,
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S86_OpDecodeType_ANDImmediateToAccum,
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S86_InstructionType_TESTRegOrMemAndReg,
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S86_OpDecodeType_TESTRegOrMemAndReg,
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S86_InstructionType_TESTImmediateAndRegOrMem,
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S86_OpDecodeType_TESTImmediateAndRegOrMem,
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S86_InstructionType_TESTImmediateAndAccum,
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S86_OpDecodeType_TESTImmediateAndAccum,
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S86_InstructionType_ORRegOrMemAndRegToEither,
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S86_OpDecodeType_ORRegOrMemAndRegToEither,
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S86_InstructionType_ORImmediateToRegOrMem,
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S86_OpDecodeType_ORImmediateToRegOrMem,
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S86_InstructionType_ORImmediateToAccum,
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S86_OpDecodeType_ORImmediateToAccum,
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S86_InstructionType_XORRegOrMemAndRegToEither,
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S86_OpDecodeType_XORRegOrMemAndRegToEither,
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S86_InstructionType_XORImmediateToRegOrMem,
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S86_OpDecodeType_XORImmediateToRegOrMem,
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S86_InstructionType_XORImmediateToAccum,
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S86_OpDecodeType_XORImmediateToAccum,
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S86_InstructionType_REP,
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S86_OpDecodeType_REP,
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S86_InstructionType_CALLDirectWithinSeg,
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S86_OpDecodeType_CALLDirectWithinSeg,
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S86_InstructionType_CALLIndirectWithinSeg,
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S86_OpDecodeType_CALLIndirectWithinSeg,
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S86_InstructionType_CALLDirectInterSeg,
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S86_OpDecodeType_CALLDirectInterSeg,
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S86_InstructionType_CALLIndirectInterSeg,
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S86_OpDecodeType_CALLIndirectInterSeg,
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S86_InstructionType_JMPDirectWithinSeg,
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S86_OpDecodeType_JMPDirectWithinSeg,
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S86_InstructionType_JMPDirectWithinSegShort,
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S86_OpDecodeType_JMPDirectWithinSegShort,
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S86_InstructionType_JMPIndirectWithinSeg,
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S86_OpDecodeType_JMPIndirectWithinSeg,
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S86_InstructionType_JMPDirectInterSeg,
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S86_OpDecodeType_JMPDirectInterSeg,
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S86_InstructionType_JMPIndirectInterSeg,
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S86_OpDecodeType_JMPIndirectInterSeg,
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S86_InstructionType_RETWithinSeg,
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S86_OpDecodeType_RETWithinSeg,
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S86_InstructionType_RETWithinSegAddImmediateToSP,
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S86_OpDecodeType_RETWithinSegAddImmediateToSP,
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S86_InstructionType_RETInterSeg,
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S86_OpDecodeType_RETInterSeg,
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S86_InstructionType_RETInterSegAddImmediateToSP,
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S86_OpDecodeType_RETInterSegAddImmediateToSP,
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S86_InstructionType_JE_JZ,
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S86_OpDecodeType_JE_JZ,
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S86_InstructionType_JL_JNGE,
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S86_OpDecodeType_JL_JNGE,
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S86_InstructionType_JLE_JNG,
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S86_OpDecodeType_JLE_JNG,
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S86_InstructionType_JB_JNAE,
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S86_OpDecodeType_JB_JNAE,
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S86_InstructionType_JBE_JNA,
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S86_OpDecodeType_JBE_JNA,
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S86_InstructionType_JP_JPE,
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S86_OpDecodeType_JP_JPE,
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S86_InstructionType_JO,
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S86_OpDecodeType_JO,
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S86_InstructionType_JS,
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S86_OpDecodeType_JS,
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S86_InstructionType_JNE_JNZ,
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S86_OpDecodeType_JNE_JNZ,
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S86_InstructionType_JNL_JGE,
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S86_OpDecodeType_JNL_JGE,
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S86_InstructionType_JNLE_JG,
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S86_OpDecodeType_JNLE_JG,
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S86_InstructionType_JNB_JAE,
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S86_OpDecodeType_JNB_JAE,
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S86_InstructionType_JNBE_JA,
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S86_OpDecodeType_JNBE_JA,
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S86_InstructionType_JNP_JO,
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S86_OpDecodeType_JNP_JO,
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S86_InstructionType_JNO,
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S86_OpDecodeType_JNO,
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S86_InstructionType_JNS,
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S86_OpDecodeType_JNS,
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S86_InstructionType_LOOP,
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S86_OpDecodeType_LOOP,
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S86_InstructionType_LOOPZ_LOOPE,
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S86_OpDecodeType_LOOPZ_LOOPE,
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S86_InstructionType_LOOPNZ_LOOPNE,
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S86_OpDecodeType_LOOPNZ_LOOPNE,
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S86_InstructionType_JCXZ,
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S86_OpDecodeType_JCXZ,
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S86_InstructionType_INT,
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S86_OpDecodeType_INT,
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S86_InstructionType_INT3,
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S86_OpDecodeType_INT3,
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S86_InstructionType_INTO,
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S86_OpDecodeType_INTO,
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S86_InstructionType_IRET,
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S86_OpDecodeType_IRET,
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S86_InstructionType_CLC,
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S86_OpDecodeType_CLC,
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S86_InstructionType_CMC,
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S86_OpDecodeType_CMC,
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S86_InstructionType_STC,
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S86_OpDecodeType_STC,
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S86_InstructionType_CLD,
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S86_OpDecodeType_CLD,
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S86_InstructionType_STD,
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S86_OpDecodeType_STD,
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S86_InstructionType_CLI,
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S86_OpDecodeType_CLI,
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S86_InstructionType_STI,
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S86_OpDecodeType_STI,
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S86_InstructionType_HLT,
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S86_OpDecodeType_HLT,
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S86_InstructionType_WAIT,
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S86_OpDecodeType_WAIT,
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S86_InstructionType_LOCK,
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S86_OpDecodeType_LOCK,
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S86_InstructionType_SEGMENT,
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S86_OpDecodeType_SEGMENT,
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S86_InstructionType_Count,
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S86_OpDecodeType_Count,
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} S86_InstructionType;
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} S86_OpDecodeType;
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typedef enum S86_Mnemonic {
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S86_Mnemonic_MOV,
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S86_Mnemonic_PUSH,
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S86_Mnemonic_POP,
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S86_Mnemonic_XCHG,
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S86_Mnemonic_IN,
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S86_Mnemonic_OUT,
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S86_Mnemonic_XLAT,
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S86_Mnemonic_LEA,
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S86_Mnemonic_LDS,
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S86_Mnemonic_LES,
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S86_Mnemonic_LAHF,
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S86_Mnemonic_SAHF,
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S86_Mnemonic_PUSHF,
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S86_Mnemonic_POPF,
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S86_Mnemonic_ADD,
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S86_Mnemonic_ADC,
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S86_Mnemonic_INC,
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S86_Mnemonic_AAA,
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S86_Mnemonic_DAA,
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S86_Mnemonic_SUB,
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S86_Mnemonic_SBB,
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S86_Mnemonic_DEC,
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S86_Mnemonic_NEG,
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S86_Mnemonic_CMP,
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S86_Mnemonic_AAS,
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S86_Mnemonic_DAS,
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S86_Mnemonic_MUL,
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S86_Mnemonic_IMUL,
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S86_Mnemonic_AAM,
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S86_Mnemonic_DIV,
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S86_Mnemonic_IDIV,
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S86_Mnemonic_AAD,
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S86_Mnemonic_CBW,
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S86_Mnemonic_CWD,
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S86_Mnemonic_NOT,
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S86_Mnemonic_SHL_SAL,
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S86_Mnemonic_SHR,
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S86_Mnemonic_SAR,
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S86_Mnemonic_ROL,
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S86_Mnemonic_ROR,
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S86_Mnemonic_RCL,
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S86_Mnemonic_RCR,
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S86_Mnemonic_AND,
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S86_Mnemonic_TEST,
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S86_Mnemonic_OR,
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S86_Mnemonic_XOR,
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S86_Mnemonic_REP,
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S86_Mnemonic_CALL,
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S86_Mnemonic_JMP,
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S86_Mnemonic_RET,
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S86_Mnemonic_JE_JZ,
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S86_Mnemonic_JL_JNGE,
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S86_Mnemonic_JLE_JNG,
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S86_Mnemonic_JB_JNAE,
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S86_Mnemonic_JBE_JNA,
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S86_Mnemonic_JP_JPE,
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S86_Mnemonic_JO,
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S86_Mnemonic_JS,
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S86_Mnemonic_JNE_JNZ,
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S86_Mnemonic_JNL_JGE,
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S86_Mnemonic_JNLE_JG,
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S86_Mnemonic_JNB_JAE,
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S86_Mnemonic_JNBE_JA,
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S86_Mnemonic_JNP_JO,
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S86_Mnemonic_JNO,
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S86_Mnemonic_JNS,
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S86_Mnemonic_LOOP,
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S86_Mnemonic_LOOPZ_LOOPE,
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S86_Mnemonic_LOOPNZ_LOOPNE,
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S86_Mnemonic_JCXZ,
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S86_Mnemonic_INT,
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S86_Mnemonic_INT3,
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S86_Mnemonic_INTO,
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S86_Mnemonic_IRET,
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S86_Mnemonic_CLC,
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S86_Mnemonic_CMC,
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S86_Mnemonic_STC,
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S86_Mnemonic_CLD,
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S86_Mnemonic_STD,
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S86_Mnemonic_CLI,
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S86_Mnemonic_STI,
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S86_Mnemonic_HLT,
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S86_Mnemonic_WAIT,
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S86_Mnemonic_LOCK,
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S86_Mnemonic_SEGMENT,
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} S86_Mnemonic;
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/// Bit patterns and masks for decoding 8086 assembly. 8086 opcodes can be up
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/// Bit patterns and masks for decoding 8086 assembly. 8086 opcodes can be up
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/// to 2 bytes long and mixed with instruction specific control bits. These
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/// to 2 bytes long and mixed with instruction specific control bits. These
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@ -170,59 +258,56 @@ typedef enum S86_InstructionType {
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///
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///
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/// Instructions that do not have opcode bits in the 2nd byte will have the mask
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/// Instructions that do not have opcode bits in the 2nd byte will have the mask
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/// set to 0.
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/// set to 0.
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typedef struct S86_Instruction {
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typedef struct S86_OpDecode {
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uint8_t op_mask0;
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S86_Mnemonic mnemonic;
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uint8_t op_bits0;
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uint8_t op_mask0;
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uint8_t op_mask1;
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uint8_t op_bits0;
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uint8_t op_bits1;
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uint8_t op_mask1;
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S86_Str8 mnemonic;
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uint8_t op_bits1;
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} S86_Instruction;
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} S86_OpDecode;
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typedef enum S86_RegisterType {
|
typedef enum S86_MnemonicOp {
|
||||||
S86_RegisterType_AL,
|
S86_MnemonicOp_Invalid,
|
||||||
S86_RegisterType_CL,
|
S86_MnemonicOp_AL,
|
||||||
S86_RegisterType_DL,
|
S86_MnemonicOp_CL,
|
||||||
S86_RegisterType_BL,
|
S86_MnemonicOp_DL,
|
||||||
S86_RegisterType_AH,
|
S86_MnemonicOp_BL,
|
||||||
S86_RegisterType_CH,
|
S86_MnemonicOp_AH,
|
||||||
S86_RegisterType_DH,
|
S86_MnemonicOp_CH,
|
||||||
S86_RegisterType_BH,
|
S86_MnemonicOp_DH,
|
||||||
|
S86_MnemonicOp_BH,
|
||||||
|
|
||||||
S86_RegisterType_AX,
|
S86_MnemonicOp_AX,
|
||||||
S86_RegisterType_CX,
|
S86_MnemonicOp_CX,
|
||||||
S86_RegisterType_DX,
|
S86_MnemonicOp_DX,
|
||||||
S86_RegisterType_BX,
|
S86_MnemonicOp_BX,
|
||||||
S86_RegisterType_SP,
|
S86_MnemonicOp_SP,
|
||||||
S86_RegisterType_BP,
|
S86_MnemonicOp_BP,
|
||||||
S86_RegisterType_SI,
|
S86_MnemonicOp_SI,
|
||||||
S86_RegisterType_DI,
|
S86_MnemonicOp_DI,
|
||||||
|
|
||||||
S86_RegisterType_BX_SI,
|
S86_MnemonicOp_BX_SI,
|
||||||
S86_RegisterType_BX_DI,
|
S86_MnemonicOp_BX_DI,
|
||||||
S86_RegisterType_BP_SI,
|
S86_MnemonicOp_BP_SI,
|
||||||
S86_RegisterType_BP_DI,
|
S86_MnemonicOp_BP_DI,
|
||||||
|
|
||||||
S86_RegisterType_DirectAddress,
|
S86_MnemonicOp_DirectAddress,
|
||||||
S86_RegisterType_Immediate,
|
S86_MnemonicOp_Immediate,
|
||||||
} S86_RegisterType;
|
|
||||||
|
|
||||||
typedef enum S86_SegmentRegisterType {
|
S86_MnemonicOp_ES,
|
||||||
S86_SegmentRegisterType_Invalid,
|
S86_MnemonicOp_CS,
|
||||||
S86_SegmentRegisterType_ES,
|
S86_MnemonicOp_SS,
|
||||||
S86_SegmentRegisterType_CS,
|
S86_MnemonicOp_DS,
|
||||||
S86_SegmentRegisterType_SS,
|
|
||||||
S86_SegmentRegisterType_DS,
|
|
||||||
S86_SegmentRegisterType_Count,
|
|
||||||
} S86_SegmentRegisterType;
|
|
||||||
|
|
||||||
typedef struct S86_EffectiveAddressStr8 {
|
S86_MnemonicOp_MOVS,
|
||||||
S86_SegmentRegisterType seg_reg_type;
|
S86_MnemonicOp_CMPS,
|
||||||
S86_RegisterType reg_type;
|
S86_MnemonicOp_SCAS,
|
||||||
int32_t displacement;
|
S86_MnemonicOp_LODS,
|
||||||
char data[32];
|
S86_MnemonicOp_STOS,
|
||||||
size_t size;
|
|
||||||
bool has_displacement;
|
S86_MnemonicOp_DirectInterSegment,
|
||||||
} S86_EffectiveAddressStr8;
|
S86_MnemonicOp_Jump,
|
||||||
|
} S86_MnemonicOp;
|
||||||
|
|
||||||
typedef enum S86_EffectiveAddress {
|
typedef enum S86_EffectiveAddress {
|
||||||
S86_EffectiveAddress_None,
|
S86_EffectiveAddress_None,
|
||||||
@ -236,19 +321,25 @@ typedef enum S86_WidePrefix {
|
|||||||
S86_WidePrefix_Dest,
|
S86_WidePrefix_Dest,
|
||||||
} S86_WidePrefix;
|
} S86_WidePrefix;
|
||||||
|
|
||||||
|
typedef struct S86_Opcode {
|
||||||
|
S86_Mnemonic mnemonic; ///< Mnemonic type
|
||||||
|
S86_EffectiveAddress effective_addr; ///< Src/dest op is an effective address calculation
|
||||||
|
bool effective_addr_loads_mem; ///< Effective address uses '[]' notation to load address memory
|
||||||
|
bool lock_prefix; ///< Prefix the opcode with "lock" instruction
|
||||||
|
bool rep_prefix; ///< Prefix the opcode with "rep" instruction
|
||||||
|
bool wide; ///< Opcode has the 'w' flag set
|
||||||
|
S86_WidePrefix wide_prefix; ///< Mnemonic src/dest op requires a 'word' or 'byte' prefix (e.g. ambiguous immediate size)
|
||||||
|
S86_MnemonicOp src; ///< Source op for the mnemonic
|
||||||
|
S86_MnemonicOp dest; ///< Destination op for the mnemonic
|
||||||
|
int32_t displacement; ///< Opcode has displacement/data/offset
|
||||||
|
int32_t immediate; ///< Immediate value when src/dest op is an immediate
|
||||||
|
S86_MnemonicOp seg_reg_prefix; ///< Segment register that should prefix the upcoming instruction
|
||||||
|
} S86_Opcode;
|
||||||
|
|
||||||
typedef struct S86_AsmOp {
|
S86_Str8 S86_MnemonicStr8 (S86_Mnemonic type);
|
||||||
bool effective_addr_wide_prefix;
|
S86_MnemonicOp S86_MnemonicOpFromWReg (bool w, uint8_t reg);
|
||||||
S86_EffectiveAddress effective_addr;
|
S86_MnemonicOp S86_MnemonicOpFromSR (uint8_t sr);
|
||||||
bool has_displacement;
|
S86_Str8 S86_MnemonicOpStr8 (S86_MnemonicOp type);
|
||||||
bool lock;
|
void S86_PrintOpcodeMnemonicOp(S86_Opcode opcode, bool src);
|
||||||
bool wide;
|
void S86_PrintOpcode (S86_Opcode opcode);
|
||||||
S86_WidePrefix wide_prefix;
|
void S86_DecodeEffectiveAddr (S86_Opcode *opcode, S86_BufferIterator *it, uint8_t rm, uint8_t mod, uint8_t w);
|
||||||
S86_RegisterType src;
|
|
||||||
S86_RegisterType dest;
|
|
||||||
int32_t displacement;
|
|
||||||
int32_t immediate;
|
|
||||||
S86_SegmentRegisterType seg_reg;
|
|
||||||
} S86_AsmOp;
|
|
||||||
|
|
||||||
S86_EffectiveAddressStr8 S86_EffectiveAddressCalc(S86_BufferIterator *buffer_it, uint8_t rm, uint8_t mod, uint8_t w, S86_SegmentRegisterType seg_reg);
|
|
||||||
|
|||||||
BIN
project.rdbg
BIN
project.rdbg
Binary file not shown.
Loading…
Reference in New Issue
Block a user