perfaware/part1: Add support for L[EA|DS|ES], [L|S]AHF, P[USH|OP]F
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@ -96,6 +96,14 @@ typedef enum S86_InstructionType {
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S86_InstructionType_XLAT,
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S86_InstructionType_LEA,
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S86_InstructionType_LDS,
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S86_InstructionType_LES,
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S86_InstructionType_LAHF,
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S86_InstructionType_SAHF,
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S86_InstructionType_PUSHF,
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S86_InstructionType_POPF,
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S86_InstructionType_ADDRegOrMemToOrFromReg,
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S86_InstructionType_ADDImmediateToRegOrMem,
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S86_InstructionType_ADDImmediateToAccum,
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@ -477,6 +485,21 @@ int main(int argc, char **argv)
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[S86_InstructionType_XLAT] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1101'0111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("xlat")},
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[S86_InstructionType_LEA] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1000'1101, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("lea")},
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[S86_InstructionType_LDS] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1100'0101, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("lds")},
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[S86_InstructionType_LES] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1100'0100, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("les")},
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[S86_InstructionType_LAHF] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1111, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("lahf")},
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[S86_InstructionType_SAHF] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1110, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("sahf")},
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[S86_InstructionType_PUSHF] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1100, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("pushf")},
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[S86_InstructionType_POPF] = {.op_mask0 = 0b1111'1111, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b1001'1101, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("popf")},
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[S86_InstructionType_ADDRegOrMemToOrFromReg] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0000'0000,
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.op_bits0 = 0b0000'0000, .op_bits1 = 0b0000'0000, .mnemonic = S86_STR8("add")},
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[S86_InstructionType_ADDImmediateToRegOrMem] = {.op_mask0 = 0b1111'1100, .op_mask1 = 0b0011'1000,
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@ -627,6 +650,9 @@ int main(int argc, char **argv)
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S86_PrintLnFmt(" %.*s", S86_STR8_FMT(reg_name));
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} break;
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case S86_InstructionType_LEA: /*FALLTHRU*/
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case S86_InstructionType_LDS: /*FALLTHRU*/
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case S86_InstructionType_LES: /*FALLTHRU*/
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case S86_InstructionType_XCHGRegOrMemWithReg: /*FALLTHRU*/
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case S86_InstructionType_CMPRegOrMemAndReg: /*FALLTHRU*/
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case S86_InstructionType_SUBRegOrMemToOrFromReg: /*FALLTHRU*/
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@ -636,11 +662,20 @@ int main(int argc, char **argv)
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S86_ASSERT(op_code_size == 1);
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op_code_bytes[op_code_size++] = S86_BufferIteratorNextByte(&buffer_it);
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uint8_t d = instruction_type == S86_InstructionType_XCHGRegOrMemWithReg
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? 0
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: (op_code_bytes[0] & 0b0000'0010) >> 1;
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uint8_t w = (op_code_bytes[0] & 0b0000'0001) >> 0;
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uint8_t d = (op_code_bytes[0] & 0b0000'0010) >> 1;
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if (instruction_type == S86_InstructionType_XCHGRegOrMemWithReg ||
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instruction_type == S86_InstructionType_LEA ||
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instruction_type == S86_InstructionType_LDS ||
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instruction_type == S86_InstructionType_LES) {
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if (instruction_type == S86_InstructionType_XCHGRegOrMemWithReg) {
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d = 0; // Destination is always the memory address
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} else {
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d = 1; // Destination is always the register
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w = 1; // Always 16 bit (load into register)
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}
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}
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uint8_t mod = (op_code_bytes[1] & 0b1100'0000) >> 6;
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uint8_t reg = (op_code_bytes[1] & 0b0011'1000) >> 3;
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uint8_t rm = (op_code_bytes[1] & 0b0000'0111) >> 0;
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@ -829,7 +864,11 @@ int main(int argc, char **argv)
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sign = '-';
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}
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S86_PrintLnFmt(" $+2%c%d", sign, jump_offset);
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} else if (instruction_type == S86_InstructionType_XLAT) {
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} else if (instruction_type == S86_InstructionType_XLAT ||
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instruction_type == S86_InstructionType_LAHF ||
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instruction_type == S86_InstructionType_SAHF ||
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instruction_type == S86_InstructionType_PUSHF ||
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instruction_type == S86_InstructionType_POPF) {
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// NOTE: Mnemonic instruction only, already printed
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S86_Print(S86_STR8("\n"));
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} else {
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